Jul 20, 2023

Fork of TimberWolf, a placement tool in VLSI design

graywolf is a fork of TimberWolf 6.3.5

TimberWolf was developed at Yale University, and was distributed as open source for a time until it was taken commercial. The last open-source version of TimberWolf does not perform detail routing, but is a professional-grade placement tool. In order to continue improving the open-source version, graywolf has been forked off from version 6.3.5 of TimberWolf.

The main improvement in graywolf is that the build process is more streamlined and that it behaves as a normal linux tool - you can call it from anywhere and no environment variables must be set first.

Checkout these related ports:
  • Zcad - Simple CAD program
  • Z88 - Compact Finite Element Analysis System
  • Yosys - Yosys Open SYnthesis Suite
  • Yosys-systemverilog - SystemVerilog support for Yosys
  • Xyce - Xyce electronic simulator
  • Xcircuit - X11 circuit schematics drawing program
  • Veryl - Veryl A modern Hardware Description Language (HDL)
  • Veroroute - PCB (printed circuit board) design software
  • Verilog-mode.el - Emacs lisp modules for the Verilog language
  • Verilator - Synthesizable Verilog to C++ compiler
  • Uranium - Python framework for 3D printing applications
  • Uhdm - Universal Hardware Data Model
  • Tochnog - Free explicit/implicit Finite Element Program
  • Tkgate - Event driven digital circuit simulator
  • Sweethome3d - Free interior 3D design application