Veryl: A modern Hardware Description Language (HDL)
Veryl is a modern hardware description language. This project is under the exploration phase of language design. Features: * Symplified syntax * Based on SystemVerilog / Rust * Transpiler to SystemVerilog * Human readable output * Interoperability with SystemVerilog * Integrated Tools * Semantic checker * Source code formatter * Language server
$
pkg install verylOrigin
cad/veryl
Size
27.4MiB
License
MIT, APACHE20
Maintainer
yuri@FreeBSD.org
Dependencies
0 packages
Required by
0 packages