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veryl

0.17.2cad

Veryl: A modern Hardware Description Language (HDL)

Veryl is a modern hardware description language. This project is under the exploration phase of language design. Features: * Symplified syntax * Based on SystemVerilog / Rust * Transpiler to SystemVerilog * Human readable output * Interoperability with SystemVerilog * Integrated Tools * Semantic checker * Source code formatter * Language server

Origin
cad/veryl
Size
27.4MiB
License
MIT, APACHE20
Maintainer
yuri@FreeBSD.org
Dependencies
0 packages
Required by
0 packages