- Introduction to FreeBSD Security Best Practices
- Working with Package Management in FreeBSD
- Understanding FreeBSD Security Advisories and Updates
- Troubleshooting Common System Administration Issues in FreeBSD
- Tips for Hardening FreeBSD to achieve System Protection
- Setting Up DHCP Server in FreeBSD
- Secure User and Group Management in FreeBSD Systems
- Secure Remote Access with SSH in FreeBSD
- Optimizing System Performance in FreeBSD
- Network Packet Capture with tcpdump in FreeBSD
- All posts ...
Do you have GDPR compliance issues ?
Check out Legiscope a GDPR compliance software, that will save you weeks of work, automating your documentation, the training of your teams and all processes you need to keep your organisation compliant with privacy regulations
Jul 20, 2023
Building point for Verilog support in the Perl language
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes
- VerilogGetopt which parses command line options similar to C++ and VCS.
- VerilogLanguage which knows the language keywords and parses numbers.
- VerilogNetlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules.
- VerilogParser invokes callbacks for language tokens.
- VerilogPreproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files.
- vpassert inserts PLIish warnings and assertions for any simulator.
- vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
- vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes.
Checkout these related ports:
- Zcad - Simple CAD program
- Z88 - Compact Finite Element Analysis System
- Yosys - Yosys Open SYnthesis Suite
- Yosys-systemverilog - SystemVerilog support for Yosys
- Xyce - Xyce electronic simulator
- Xcircuit - X11 circuit schematics drawing program
- Veryl - Veryl A modern Hardware Description Language (HDL)
- Veroroute - PCB (printed circuit board) design software
- Verilog-mode.el - Emacs lisp modules for the Verilog language
- Verilator - Synthesizable Verilog to C++ compiler
- Uranium - Python framework for 3D printing applications
- Uhdm - Universal Hardware Data Model
- Tochnog - Free explicit/implicit Finite Element Program
- Tkgate - Event driven digital circuit simulator
- Sweethome3d - Free interior 3D design application