yosys
0.60Yosys Open SYnthesis Suite
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Origin: cad/yosys
Category: cad
Size: 30.7MiB
License: ISCL
Maintainer: yuri@FreeBSD.org
Dependencies: 9 packages
Required by: 3 packages
Website: yosyshq.net/yosys
$
pkg install yosysDependencies (9)
Required By (3 packages)
More in cad
opencascade7.9.3_2
Open CASCADE Technology, 3D modeling & numerical simulationscotch6.0.4.a7_6
Package for graph and mesh partitioning and sparse matrix orderingcsxcad0.6.3_7
C++ library to describe geometrical objectskicad9.0.7,2
Schematic and PCB editing softwarekicad-develr20251216162640_1
Schematic and PCB editing softwarelibrnd4.4.0
Flexible, modular two-dimensional CAD enginengspice_rework-shlib44.2
Mixed-signal circuit simulator derived from Spice and Cidergtkwave3.3.126
Electronic Waveform Vieweriverilog12.0_2
Verilog simulation and synthesis toolldraw20220211,1
LDraw-format CAD files representing many of LEGO bricks produced