silice
g20221229_1Language that simplifies prototyping and writing algorithms for FPGAs
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Origin: cad/silice
Category: cad
Size: 3.41MiB
License: GPLv3
Maintainer: yuri@FreeBSD.org
Dependencies: 3 packages
Required by: 0 packages
Website: github.com/sylefeb/Silice
$
pkg install siliceDependencies (3)
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