hs-verismith
1.1.0_1Verilog fuzzer
verismith is a Verilog fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Origin: cad/hs-verismith
Category: cad
Size: 41.0MiB
License: GPLv3
Maintainer: yuri@FreeBSD.org
Dependencies: 2 packages
Required by: 0 packages
Website: github.com/ymherklotz/verismith
$
pkg install hs-verismithDependencies (2)
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