The FreeBSD Ports Archive
FreeBSD cad  : iverilog
A Verilog simulation and synthesis tool
Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code writen in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
http://www.icarus.com/eda/verilog/
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iverilog history
v. 1.29
date: 2007/10/17 10:12:25; author: ade; state: Exp; lines: +2 -1
Migration from bison 1.x to 2.x
PR: 117086
Tested by: -exp runs
v. 1.28
date: 2007/09/13 13:50:37; author: stas; state: Exp; lines: +1 -1
- Update to 0.8.5.
v. 1.27
date: 2007/04/03 23:00:42; author: stas; state: Exp; lines: +1 -1
- Update to 0.8.4.
v. 1.26
date: 2006/11/01 23:28:09; author: stas; state: Exp; lines: +1 -1
- Update to 0.8.3
v. 1.25
date: 2006/10/03 13:34:22; author: stas; state: Exp; lines: +5 -5
- Update to 0.8.2
- Fix compiling with gcc 4.1
- Change my email
Approved by: sem (mentor)
v. 1.24
date: 2006/09/06 10:47:58; author: itetcu; state: Exp; lines: +1 -1
Stanislav wants to maintain this ports.
Requested by: Stanislav (on IRC)
v. 1.23
date: 2006/09/06 01:48:04; author: linimon; state: Exp; lines: +1 -1
Reset inactive maintainer who has not responded to email.
Hat: portmgr
v. 1.22
date: 2005/11/09 21:36:06; author: mnag; state: Exp; lines: +5 -3
Update to 0.8.1
Add second MASTER_SITES
Add SHA256
PR: 88749
Submitted by: Joachim Strombergson (maintainer)
v. 1.21
date: 2005/10/12 06:25:10; author: linimon; state: Exp; lines: +1 -1
Update maintainer's email address.
v. 1.20
date: 2004/11/05 13:16:52; author: arved; state: Exp; lines: +3 -3
Update to 0.8
PR: 72949
Submitted by: Joachim Strombergson
v. 1.19
date: 2004/07/04 15:53:09; author: nobutaka; state: Exp; lines: +2 -2
Update to 0.7.20040606.
PR: ports/68643
Submitted by: maintainer
v. 1.18
date: 2004/03/18 22:19:00; author: krion; state: Exp; lines: +2 -3
- Update to version 20040220
PR: ports/64432
Submitted by: maintainer
v. 1.17
date: 2004/02/04 05:18:52; author: marcus; state: Exp; lines: +1 -0
Bump PORTREVISION on all ports that depend on gettext to aid with upgrading.
(Part 2)
v. 1.16
date: 2004/01/30 10:30:07; author: linimon; state: Exp; lines: +1 -7
Unbreak on 4.x.
PR: ports/62073
Submitted by: Hiroki Sato
v. 1.15
date: 2003/12/17 16:02:50; author: linimon; state: Exp; lines: +10 -6
Update to 20031202 snapshot. Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt:
Combination 64bit/32bit runtime support now works fully on AMD64
systems; wait on lists of named events now works; there is no
longer a common iverilog.conf, instead there are target specific
foo.conf files with a new and cleaner format; 64bit values are more
portably handled; several synthesis bugs related to the control inputs
of flip-flops have been fixed.
Committer is marking this BROKEN on 4.x while we investigate install
problems. It works on 5.x only for now.
PR: ports/60162
Submitted by: Joachim Strombergson (maintainer)
v. 1.14
date: 2003/11/20 03:19:37; author: linimon; state: Exp; lines: +2 -0
Mark as broken while we muddle through the compile problem with
the author.
v. 1.13
date: 2003/10/27 10:02:34; author: linimon; state: Exp; lines: +2 -4
Maintainer Update to latest snapshot. Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320
v. 1.12
date: 2003/10/17 08:26:42; author: linimon; state: Exp; lines: +5 -3
Maintainer update to snapshot version. In addition to fixing the port
for gcc3.3, 10 months of updates are included:
- Rework expression parsing and elaboration to accomodate real/realtime
values and expressions.
- Calculate delay statement delays using elaborated expressions instead
of pre-elaborated expression trees.
- Implement the wait statement behaviorally instead of as nets.
- Support event names as expression elements.
- Fix configuration errors, spelling errors, clarification of certain
objects.
See internal v. logs in each file for more elaboration.
v. 1.11
date: 2003/05/19 08:24:55; author: keichii; state: Exp; lines: +1 -1
Change the Maintainer to someone who uses this port more than I do.
v. 1.10
date: 2003/05/17 03:17:55; author: will; state: Exp; lines: +3 -4
Fix MAN. This commit completes changes submitted in the PR. I made
the earlier changes unaware that the submitter had sent the PR.
PR: 51989
Submitted by: Ports Fury
v. 1.9
date: 2003/05/16 18:18:38; author: will; state: Exp; lines: +0 -2
Fix this port and remove BROKEN.
v. 1.8
date: 2003/05/06 07:19:02; author: kris; state: Exp; lines: +2 -0
BROKEN: Does not install
v. 1.7
date: 2003/03/07 05:56:59; author: ade; state: Exp; lines: +1 -0
Clear moonlight beckons.
Requiem mors pacem pkg-comment,
And be calm ports tree.
E Nomini Patri, E Fili, E Spiritu Sancti.
v. 1.6
date: 2003/01/31 17:49:45; author: keichii; state: Exp; lines: +1 -1
Update to iverilog 0.7
Submitted by: Joachim Str?mbergson
v. 1.5
date: 2002/09/19 03:04:23; author: kris; state: Exp; lines: +1 -1
Add missing files
v. 1.4
date: 2002/03/04 00:46:10; author: keichii; state: Exp; lines: +2 -2
Update to 0.6 after my long absence
PR: 35317
Submitted by: Joachim Strömbergson
v. 1.3
date: 2001/05/18 16:01:46; author: ijliao; state: Exp; lines: +2 -2
pass maintainership to keichii
v. 1.2
date: 2001/02/22 04:58:04; author: ijliao; state: Exp; lines: +2 -1
forgot bison dependence
v. 1.1
date: 2001/02/13 11:02:14; author: ijliao; state: Exp;
add iverilog, a Verilog simulation and synthesis tool
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