The FreeBSD Ports Archive

FreeBSD cad : gplcver

A Verilog HDL simulator

 GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
implements some of the 2001 P1364 standard features including all three
PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
Reference Manual (LRM).

Verilog is the name for both a language for describing electronic hardware
called a hardware description language (HDL) and the name of the program
that simulates HDL circuit descriptions to verify that described circuits
will function correctly when the are constructed. Verilog is used only for
describing digital logic circuits. Other HDLs such as Spice are used for
describing analog circuits. There is an IEEE standard named P1364 that
standardizes the Verilog HDL and the behavior of Verilog simulators.
Verilog is officially defined in the IEEE P1364 Language Reference
Manual (LRM) that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach digital circuit
design using Verilog. 

gplcver history

v. 1.8
date: 2007/08/23 03:59:55;  author: tabthorpe;  state: Exp;  lines: +1 -1
- change maintainer address on ports I maintain

Approved by:	clsung (mentor)

v. 1.7
date: 2007/07/21 01:21:52;  author: ijliao;  state: Exp;  lines: +1 -1
'actually' pass maintainership

v. 1.6
date: 2007/07/21 01:20:50;  author: ijliao;  state: Exp;  lines: +1 -1
upgrade to 2.12.a
pass maintainership to submitter

PR:		114768
Submitted by:	Thomas Abthorpe 

v. 1.5
date: 2006/08/03 03:26:38;  author: clsung;  state: Exp;  lines: +1 -1
- maintainer is a committer

v. 1.4
date: 2006/01/20 14:18:34;  author: arved;  state: Exp;  lines: +0 -4
Fix build on sparc

v. 1.3
date: 2006/01/19 23:31:12;  author: kris;  state: Exp;  lines: +7 -1
BROKEN on sparc64: Does not compile

v. 1.2
date: 2006/01/04 05:56:54;  author: edwin;  state: Exp;  lines: +1 -1
Fix maintainership (set to submitter)

v. 1.1
date: 2005/12/29 03:48:58;  author: edwin;  state: Exp;
[NEW PORT] cad/gplcver: A Verilog HDL simulator

	GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
	It also implements some of the 2001 P1364 standard features
	including all three PLI interfaces (tf_, acc_ and vpi_) as
	defined in the 2001 Language Reference Manual (LRM).

	Verilog is the name for both a language for describing
	electronic hardware called a hardware description language
	(HDL) and the name of the program that simulates HDL circuit
	descriptions to verify that described circuits will function
	correctly when the are constructed. Verilog is used only
	for describing digital logic circuits. Other HDLs such as
	Spice are used for describing analog circuits. There is an
	IEEE standard named P1364 that standardizes the Verilog HDL
	and the behavior of Verilog simulators.  Verilog is officially
	defined in the IEEE P1364 Language Reference Manual (LRM)
	that can be purchased from IEEE. There are many good books
	for learning that teach the Verilog HDL and/or that teach
	digital circuit design using Verilog.

	WWW: http://www.pragmatic-c.com/gpl-cver/

PR:		ports/80968
Submitted by:	Ying-Chieh Liao 
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